The present invention relates generally to integrated circuit memory devices and, more particularly, to a column redundancy system and method for a micro-cell eDRAM architecture.
The replacement of static random access memory (SRAM) with a wide bandwidth, embedded dynamic random access memory (eDRAM) for a high-speed, on-chip cache has become a recent trend in the semiconductor memory industry. Because DRAM is inherently smaller than SRAM, a comparatively larger DRAM cache may be installed on a chip to improve processor performance. On the other hand, the speed of a DRAM is generally inferior to that of an SRAM. Thus, in order to boost the performance of a DRAM based on-chip cache, a micro-cell eDRAM architecture may be implemented.
In a micro-cell eDRAM architecture, a DRAM array is further organized into a plurality of smaller DRAM arrays, or xe2x80x9cmicro-cellsxe2x80x9d. Each individual micro-cell may include, for example, 64 to 256 wordlines and 64 to 256 bitline pairs. Accordingly, each micro-cell array may be about 16 to 256 times smaller than a standard DRAM array. By accessing an individual DRAM micro-cell having shorter wordlines and bitline pairs (having smaller parasitic capacitances), a faster read/write operation may be achieved over a conventional array. As a result, a wide bandwidth eDRAM with a micro-cell architecture demonstrates improved performance in terms of faster cycle time and access time.
A micro-cell eDRAM design may also include one or more SRAM macros which serve as a cache interface between a plurality of eDRAM arrays and the processor. Since the size of such an SRAM macro is rough equivalent to that of a micro-cell, the area penalty is acceptable. However, a relatively wide internal bus is used to facilitate a high data transfer rate among the eDRAM arrays, the SRAM macro(s), and the processor. A small TAG memory may also be used to record the addresses of those particular micro-cells having data therefrom temporarily stored in the SRAM cache.
As is the case with a conventional eDRAM architecture, all data bits along a selected wordline of a micro-cell are accessed at once; thus, no column decoding functions are used in an eDRAM system. However, the elimination of a column decoding function in a micro-cell eDRAM architecture presents certain challenges in the column path design. Not only does the column path layout become very difficult (due to pitch limitations), but a conventional column redundancy circuit design becomes inefficient for this type of architecture.
More specifically, one challenge in the wide datawidth eDRAM design is to provide an effective column repair system for replacing defective column elements (e.g., bitlines, local and global datalines, etc.) with redundancy elements. In a conventional DRAM array, bitlines are hierarchically grouped by their column addresses, such that xe2x80x9cpartial dataxe2x80x9d accessed for a read or write command is possible. In other words, not all of the data in a given row need be transferred out. The most common column redundancy system for a conventional DRAM is to replace an entire group of bitlines (e.g., 4 bitlines per group), regardless of how many particular bitlines in that group are actually defective. However, for a wide datawidth eDRAM design as described above, all of the bitlines in a given eDRAM micro-cell are be retrieved and sent to the SRAM cache. Without a column address provided, a column redundancy operation thus becomes a difficult proposition.
The above discussed and other drawbacks and deficiencies of the prior art are overcome or alleviated by a column redundancy system for a memory array configured into a plurality of individual micro-cells. In an exemplary embodiment, the system includes a column redundancy apparatus for performing a redundancy swapping operation of column elements within the individual micro-cells. The column redundancy apparatus further includes a fuse information storage device for storing fuse information for each individual micro-cell, the fuse information indicative of the location of any defective column elements therein. A first bank address decoding mechanism decodes a read bank address corresponding to a first micro-cell accessed for a read operation, and a second bank address decoding mechanism decodes a write bank address corresponding to a second micro-cell accessed for a write operation. The second micro-cell is capable of being accessed simultaneously with the first micro-cell. In addition, a first compare circuit compares the decoded read bank address to specific fuse information corresponding to said first micro-cell, and a second compare circuit compares the decoded write bank address to specific fuse information corresponding to the second micro-cell. If the first compare circuit determines that there is at least one defective column element contained within the first micro-cell, then the column redundancy apparatus generates an internal column address corresponding to the at least one defective column element in the first micro-cell. Likewise, if the second compare circuit determines that there is at least one defective column element contained within the second micro-cell, then the column redundancy apparatus generates an internal column address corresponding to the at least one defective column element in the second micro-cell.
In a preferred embodiment, the internal column address corresponding to the at least one defective column element in said first micro-cell, if generated, is used by a read multiplexer circuit within the column redundancy apparatus to perform the redundancy swapping operation for the first micro-cell. The internal column address corresponding to the at least one defective column element in the second micro-cell, if generated, is used by a write multiplexer circuit within the column redundancy apparatus to perform the redundancy swapping operation for the second micro-cell.
In one embodiment, the plurality of individual micro-cells within the memory array are arranged into micro-cell blocks, and the fuse information storage device further includes a plurality of fuse register blocks disposed in proximity to the micro-cell blocks. In another embodiment, the fuse information storage device further includes a first static random access memory (SRAM) array which is accessed for a read operation, and a second static random access memory (SRAM) array which is being accessed for a write operation. In still another embodiment, the fuse information storage device further includes a dual port, static random access memory (SRAM) array. One port is capable of being accessed only during a read operation, and the other port is capable of being accessed during a read or a write operation.